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Logic Circuits Sequence Detector Soru Logic Circuits Sequence Detector Soru
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elimde sınava hazırlanmak için çözmem gereken 3 tane soru var
sorular bunlar:
1. Design 3-bit upper/down counter using T-FFs. It should include a control input x; if x=1, then the circuit should behave as an up counter, if x=0, then the circuit should behave as a down counter.
Hint: Counter counts up from 0 to 7, and repeats. Counter counts down from 7 to 0, and repeats. Construct the state table: Right side - Input x and present states, Left side - next states. Using excitation table for T-FF find the input values for each T-FF. Place the values to Karnaugh diagrams (4 variables) and find T-FFs' input equations. Implement the circuit using input equations.
2. Design a Mealy type FSM that acts as a sequence detector described as: FSM has an input x and an output z. Machine is a sequence detector that produces z=1 when the previous values of x were 00 or 11; otherwise z=0. Implement the FSM using JK FFs.
Hint: Draw the state diagram for the Mealy FSM (define states with letters). Construct the state table. Assign codes to the letters desribing the states (codes in terms of 0s and 1s). Replace the assigned codes to state table. Find JK-FFs input equations and output equation. Implement the circuit.
3. Design a non-sequential that goes through states 0-2-3-6-1 and repeats, using JK-FFs.
Hint: Using state diagram (0-2-3-6-1-0) derive the state table. Find the input values for each JK-FF. Derive FFs' input equations using Karnaugh diagrams. Implement the circuit.--------------------------------------------------------------------------------------------------
sorulardan 1 ve 3'ü çözdüm ama 2. soruda takıldım kaldım, anlayan biri detaylı(state diagram, state table vs.) çözümünü gösterebilirse iyi olur
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